Modern chips such as Dynamic Random Access Memory (DRAM) chips have many different voltages that have to be generated on the chip by a plurality of generators that have to be controlled as to their sequence of start-up times, etc. during various operational phases.
U.S. Pat. No. 5,319,601 (Kawata et al.), issued on Jun. 7, 1994, discloses a power supply start-up circuit for a DRAM wherein a rise time of an intermediate potential is made short after the power is switched on, and current consumption is kept low. The power supply circuit comprises both a power-on detection circuit which detects when an external power supply potential reaches a predetermined potential and produces first and second detection signals, and an internal power supply circuit which generates an internal power supply potential. The power supply circuit further comprises a first intermediate potential generating circuit which generates a first intermediate potential from the external power supply potential and supplies it to an intermediate potential supplying node. When the first detection signal is produced and the first intermediate potential reaches a predetermined potential, the first intermediate potential generating circuit stops both the supply of the first intermediate potential to the intermediate potential supplying node and the intermediate potential generating function. A second intermediate potential generating circuit generates a second intermediate potential from the internal power supply potential and, when the second detection signal is produced, supplies the second intermediate potential to the supplying node. The first intermediate potential generating circuit has a larger driving capability than that of the second intermediate generating circuit which makes possible a shortening of the rise time of the intermediate potential after the power is switched-on, and to reduce the overall current consumption.
Referring now to FIG. 1, there is shown a block diagram of a prior art generator control arrangement 10 for controlling generators that generate voltages in, for example, a Dynamic RAM (DRAM) chip. The arrangement 10 comprises a power-on circuit 20, a Generator system (GENERATORS) 22 that comprises Reference Voltage Generators (REF. VOLT.) 23 and a plurality of voltage generators (not shown), Initialization circuits 24, Pull-up circuits 26, and first and second OR gate arrangements 28 and 30, respectively. It is to be understood that the Pull-up circuits 26 and the first and second OR gate arrangements 28 and 30 comprise one or more of such circuits or gates depending on the number of signals being received and processed in parallel by the pull-up circuits 26 and OR gate arrangements 28 and 30.
Signals from Bondpads and Testpads on the associated chip are received in the Pull-up circuits 26. In the Pull-up circuits 26, an output signal is pulled up to a logic high level (logic "1") by default when an input pad is not connected, and a logic "0" is outputted if the input signal is actively pulled down from the pad or connection. The output signals from the Pull-up circuits 26 are logically combined in the first OR gate arrangement 28 with Testmode Register signals that have been initialized in associated Initialization circuits 24. The outputs from the first OR gates 28 are coupled to first inputs of the Power-On circuit 20 and to the Generator system 22. The Testmode Register signals are also initialized in associated Initialization circuits 24 and then coupled to the Generator system 22. Signals from Fuses (not shown) on the associated chip are initialized in associated Initialization circuits 24 and coupled into the Reference generators 23 of the Generator system 22. The fuse signals are also logically combined in the second OR gate arrangement 30 with the input Testmode Register signals and then coupled to the Generator system 22. The Power-On circuit 20 receives the output signals from the first OR gate arrangement 28, and various signals from the Initialization circuits 24, and generates output control signals to both the Initialization circuits 24 and to the generators of the Generator system 22. The Generator system 22 comprises a plurality of voltage generators, including the reference generators 23, and receives an External Voltage (VEXT), system signals (SYS. SIGS.), and the signals from each of the first and second OR gate arrangements 28 and 30, the Initialization circuits 24, and the Power-On circuit 20, and generates output signals to the Initialization circuits 24 and the various voltages (not shown) required by the remote circuits on the associated chip.
To control the operation of these generators, many logic control circuits are involved in the generator functions, which conventionally are performed by local logic circuits (not shown) dispersed throughout the generator system 22 within the individual generator blocks (not shown). The conventional Generator system 22 is the result of a growth process, where additional logic circuitry was added locally whenever new voltage levels and the associated generator blocks were added, or whenever control functionality needed to be changed.
It is desirable to provide an arrangement wherein control of voltage generators on a chip avoids the necessity of logic circuits being dispersed throughout the generator system, and a flexibility for accommodating any changes that may be needed for future modifications of the generator system or chip is possible.